Since the advent of integrated circuits, I/O interfaces have been used for the purpose of interfacing internal (i.e., on-chip) circuits to external (i.e., off-chip) circuits. I/O interfaces typically are designed using asynchronous circuits which operate without a clock. As the frequency of signals through the interface increases, however, it becomes more difficult to capture and transmit signals using asynchronous circuits. In an asynchronous circuit, signals ripple through the system, set and reset flip-flops, and produce an output at some unpredictable future time dependent on system propagation delays. Because signals can happen at any time, asynchronous circuits are prone to being upset by noise in the system. For example, a noise burst on a signal line between clock pulses could cause a number of flip-flops to change state and cause a system malfunction.
In contrast, synchronous circuits, such as edge-triggered "D" flip-flops, can be used to reliably capture and transmit signals on either the positive-edge or the negative-edge of a clock pulse or strobe. A noise burst on a signal line between clock pulses does not typically upset a synchronous circuit. While synchronous circuits have been included in I/O interfaces for testing purposes (e.g., scan testing), they are not typically used to capture data signals communicated between core logic and pads in an integrated circuit chip. To reliably capture such data signals, synchronous circuits must have clocks that abide by a variety of constraints including skew, duty cycle, and setup/hold times. If these clock parameters are violated, the synchronous circuits could malfunction (e.g., clock race, latch-up) resulting in erroneous data signals being captured and transmitted. To reduce the probability of synchronous circuits malfunctioning, such circuits can be designed using custom physical layouts.
Custom physical layouts place physical placement control and constraints on the components of the I/O interface so as to restrict the variability of critical parameters, thereby ensuring reliable high frequency operation. By designing components to have a tight relationship to each other, any uncertainty in the operation and/or compensation of such components can be minimized. For example, clock and data paths can be accurately matched as well as designed to compensate for simultaneous switching push-out.
In addition to reliability concerns, it is also desirable that I/O interfaces be configurable on-the-fly to comply with multiple protocols and signal specifications including: Accelerated Graphics Port (AGP), Double Data Rate (DDR), Peripheral Component Interconnect (PCI), Stob Serial Terminated Logic (SSTL), and Transistor-to-Transistor Logic (TTL). Such I/O interfaces provide additional flexibility to system designers.
Accordingly, there is a need for reliable and flexible I/O interfaces for buffering and conditioning data signals between core logic and pads in integrated circuit chips. It is desirable that these I/O interfaces be configurable on-the-fly to comply with multiple protocols and signal specifications. Such I/O interfaces should have custom physical layouts of circuitry, power, and clock bussing to eliminate problems associated with, for example, uneven layout traces.